Substrate treating system for depositing a metal gate on  a high-k dielectric film and improving high-k dielectric film and metal gate interface

ABSTRACT

An apparatus to improve high-k dielectric film and metal gate interface in the fabrication of MOSFET by depositing a metal gate on a high-k dielectric comprising an annealing step annealing a substrate with high-k dielectric film deposited thereon in a thermal annealing module and a depositing step depositing a metal gate material on said annealed substrate in a metal gate deposition module, characterized that said annealing step and depositing step are carried out consecutively without a vacuum break.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority of Japanese Patent Application No.2005-051340, filed in Japan on Feb. 25, 2005, and is a divisionalapplication of U.S. patent application Ser. No. 11/347,256, filed Feb.6, 2006, the entire contents of which are hereby incorporated byreference.

FIELD OF THE INVENTION

The present invention relates to a method for depositing a metal gate ona high-k dielectric film in the fabrication of metal-oxide-semiconductorfield effect transistors (MOSFET). And, the present invention relates toa method for improving high-k dielectric film and metal gate interfacein the fabrication of MOSFET. Also, the present invention relates to asubstrate treating system, which is suitable to be used in said methods.

BACKGROUND OF THE INVENTION

The elementary device of most of the complex integrated circuits (IC)fabricated on semiconductor substrates is a metal-oxide-semiconductor(MOS) transistor. These transistors are generally calledmetal-oxide-semiconductor field effect transistors (hereinafter referredto MOSFET).

FIG. 15 shows an example of a simple diagram of a MOSFET denoted bynumeral 100. In FIG. 15, MOSFET 100 is comprised of a semiconductor 101,gate dielectric (gate oxide) 104, gate electrode 105, source region 102and drain region 103. During its operation an electric field is appliedto the channel region 107 below the gate dielectric 104 to switch thetransistor on and off.

In order to increase the performance of integrated circuits (IC), thedesign rule or the smallest feature size of ICs are gradually reduced.With the shrink of design rule, new materials and deposition techniquesare of importance. For example, the thickness of gate oxide (t_(ox))reduces with the reduction of gate length (G_(L)) (denoted by numeral106) with the relationship of t_(ox)=0.018 G_(L). This is important tomaintain a higher capacitance between semiconductor 101 and the gateelectrode 105.

With respect to the thinning of gate oxide 104, conventional dielectricmaterials (SiO₂, SiON) are no longer applicable since very thin films ofthese materials show different electrical properties such as higherleakage current.

The gate dielectric (gate oxide) should be replaced with new dielectricmaterials of which the dielectric constant is higher than that of SiO₂.This facilitates to use thicker film without compensating thecapacitance.

These higher dielectric constant materials are called high-kdielectrics. For example, HfO₂, HfSiO, HfAlO are considered as high-kdielectrics.

With the use of high-k dielectrics, conventional gate electrodematerial, such as poly-Si, also must be replaced with differentmaterials due to two reasons. First is that poly-Si is not compatiblewith most high-k dielectrics. Second is that use of poly-Si causes ageneration of depletion region at the poly-Si/high-k interface resultingin a higher equivalent oxide thickness (EOT) and a lower capacitance.

Pure metals, metal alloys, metal nitride or metal alloy nitrides areusually considered for a gate electrode to be used with high-kdielectrics.

At present, high-k and metal gate are fabricated with the proceduregiven in the following chart, for example.

1. clean Si substrates with diluted HF solution

2. dry the wafer in Nitrogen

3. deposit thermal SiO₂ (˜1 nm)

4. deposit Hf (or HfO₂)

5. thermal annealing

6. deposit metal gate

7. thermal annealing

One may eliminate step 3 described in the above procedure, and instead,Hf or HfO₂ is directly deposited on surface-treated Si. Moreover, theabove procedure is explained using HfO₂ as the high-k dielectric.However, one can select any other high-k material as the dielectric, forexample, HfSiO, HfSiON, HfAlO etc.

FIG. 14 is a schematic diagram showing a CVD module 40 attached to acentral wafer-handling platform 3 and wafer loading/unloadingequipment-front-end module 13. CVD module 40 may be Metal OrganicChemical Vapor Deposition (MOCVD) module or Atomic Layer Deposition(ALD) module.

In MOCVD processes, metal-organic gases are used. There are two basicgroups of metal-organic gases; for example, in depositing Hf-basedielectrics one can use i) halide-based gases such as HfCI₄ or ii)carbon-based gases such as C₁₆H₄₀N₄Hf (Tetrakis-diethylamino hafnium).

In ALD depositions, two gases are alternatively introduced into the CVDmodule 40. When the first gas, which is usually called the precursorgas, is introduced into the CVD module 40, precursor molecules stick onthe substrate surface. When the second gas is introduced into the CVDmodule 40, it reacts with surface-stick precursor molecules and forms adielectric film. This procedure continues until a film with the desiredthickness is formed.

Impurity contamination is the biggest problem in any CVD (ALD or MOCVD)processes.

For example, firstly, in MOCVD, halides or carbon contaminates thewafer. In ALD process also, carbon from precursor gas contaminates thefilm. Higher impurity concentration in the dielectric film causes higherleakage current, threshold voltage shift and reduction of electronmobility in the channel region 107 in MOSFET devices (FIG. 15).

Secondly, for any CVD (MOCVD or ALD) processes, wafer must be heated toa higher temperature, for example 400° C. The temperature uniformity onthe substrate surface directly affects the film uniformity. Anytemperature non-uniformity results in non-uniform dielectric film andthereby causes faulty MOSFET devices or a lower yield (number of goodMOSFETs) per wafer.

Thirdly, lower throughput, particularly with the ALD method, limits theeconomic viability. In the ALD process, film grows with the switching oftwo gases so the deposition rate is slow. The required film thickness ofhigh-k dielectric materials is usually 10-40 angstroms. When thesedeposition rate and film thickness are considered, the throughput isless than 10 wafers per hour.

Fourth, owing to the expensive precursors and lower utilizationefficiency of precursors, CVD methods have a higher running cost. Thisalso limits the economic viability of CVD methods.

OBJECTS AND SUMMARY

In the fabrication of high-k dielectric film and metal gates, thequalities of lower interface between Si and high-k dielectric film, andupper interface between high-k dielectric film and metal gates are ofimportance.

The upper interface quality particularly affects the electron mobility,threshold voltage (V_(th)) shift due to pinning effect.

To improve the electron mobility and minimize V_(th) shift, theinterface trap density must be lowered.

The interface trap density depends on high-k dielectric and metal gatematerial qualities as well as fabrication process.

Conventionally, after the thermal annealing of high-k dielectric, whichis usually done in a separate annealing system, wafers are exposed tonormal atmosphere until they are placed in metal gate deposition system.

Usually, high-k dielectrics show a better thermal stability, however,depending on the dielectric materials, they show different chemicalproperties after being exposed to normal atmosphere.

For example, an SiO₂ layer can be grown at the Si and high-k interfacewhen HfO₂ is selected as the high-k, since oxygen diffuses through HfO₂film. The thickness of this interface SiO₂ also varies depending on thetime exposed to the normal atmosphere causing reliability issues.

If LaO or its alloys are used as high-k, moisture absorbs into the filmwhen exposed to the atmosphere; this changes trap density in the filmand interface. All these changes after being exposed to atmosphere causea decrease of film quality and thereby the performance of end-productsemiconductor devices is decreased.

Therefore, an object of the present invention is to provide a method todeposit a metal gate on a high-k dielectric film in the fabrication ofmetal-oxide-semiconductor field effect transistors (MOSFET) by which thequalities of high-k dielectric film and metal gate material are improvedthereby electron mobility is improved and V_(th) shift is minimized.

Also, another object of the present invention is to provide a method toimprove high-k dielectric film and metal gate interface in thefabrication of MOSFET by which the interface trap density can be loweredthereby electron mobility is improved and Vth shift is minimized.

A further object of the present invention is to provide a substratetreating system, which is suitable to be used in said methods.

In order to achieve the above-described objects, a first aspect of thepresent invention provides a method for depositing a metal gate on ahigh-k dielectric film in the fabrication of MOSFET comprising anannealing step annealing a substrate with high-k dielectric filmdeposited thereon in a thermal annealing module, and a depositing stepdepositing a metal gate material on said annealed substrate in a metalgate deposition module, wherein the annealing step and depositing stepare carried out consecutively without a vacuum break.

This method is conducted by a substrate treating system comprising awafer-handling platform including transfer means to transfer a substrateand a processing module connected to said wafer-handling platform,wherein said processing module includes at least a thermal annealingmodule and a metal gate deposition module, and said transfer meanstransfer the substrate between said wafer-handling platform and saidprocessing module without a vacuum break.

A second aspect of the present invention provides a method to deposit ametal gate on a high-k dielectric film in the fabrication of MOSFETcomprising an annealing step annealing a substrate with high-kdielectric film deposited thereon in a thermal annealing module, acooling step cooling said annealed substrate in a cooling module, and adepositing step depositing a metal gate material on said cooledsubstrate in a metal gate deposition module, characterized that saidannealing step, cooling step and depositing step are carried outconsecutively without a vacuum break.

This method is conducted by a substrate treating system comprising awafer-handling platform including transfer means to transfer a substrateand processing module connected to said wafer-handling platform, whereinsaid processing module includes at least a thermal annealing module, acooling module and a metal gate deposition module, and said transfermeans transfer the substrate between said wafer-handling platform andsaid processing module without a vacuum break.

A third aspect of the present invention provides a method to deposit ametal gate on a high-k dielectric film in the fabrication of MOSFETcomprising a first depositing step depositing a high-k dielectric filmon a substrate in a high-k deposition module, an annealing stepannealing said substrate on which high-k dielectric film is deposited ina thermal annealing module, a cooling step cooling said annealedsubstrate in a cooling module, and a second depositing step depositing ametal gate material on said cooled substrate in a metal gate depositionmodule characterized that said first depositing step, annealing step,cooling step and second depositing step are carried out consecutivelywithout a vacuum break.

This method is conducted by a substrate treating system comprising awafer-handling platform including transfer means to transfer a substrateand processing module connected to said wafer-handling platform, whereinsaid processing module includes at least a thermal annealing module, acooling module, a high-k deposition module, and a metal gate depositionmodule, and said transfer means transfer the substrate between saidwafer-handling platform and said processing module without a vacuumbreak.

A fourth aspect of the present invention provides a method to deposit ametal gate on a high-k dielectric film in the fabrication of MOSFETcomprising a first depositing step depositing a thin thermal SiO₂ filmon a substrate in a thermal annealing module, a first cooling stepcooling said substrate in a cooling module, a second depositing stepdepositing a high-k dielectric film on a substrate in a high-kdeposition module, an annealing step annealing said substrate in athermal annealing module, a second cooling step cooling said annealedsubstrate in a cooling module, and a third depositing step depositing ametal gate material on said cooled substrate in a metal gate depositionmodule, wherein the first depositing step, first cooling step, seconddepositing step, annealing step, second cooling step and thirddepositing step are carried out consecutively without a vacuum break.

This method is conducted by a substrate treating system comprising awafer-handling platform including transfer means to transfer a substrateand processing module connected to said wafer-handling platform, whereinsaid processing module includes at least a thermal annealing module, acooling module, a high-k deposition module, and a metal gate depositionmodule, and said transfer means transfer the substrate between saidwafer-handling platform and said processing module without a vacuumbreak.

A fifth aspect of the present invention provides a method to deposit ametal gate on a high-k dielectric film in the fabrication of MOSFETaccording to any one of the before described first to fourth aspects ofthe present invention wherein a metal gate formed by said depositingstep depositing a metal gate material comprises of a plural film stack,and after said metal gate is formed the substrate is further annealedconsecutively in the thermal annealing module without a vacuum break.

In this depositing method, the before described plural film stackincluding different films, for example, a plural film stack includingdifferent films is laminated. And, by the annealing step, which isconsecutively conducted after said metal gate material comprised of aplural film stack is formed, the metal stack materials are intermixed.

A sixth aspect of the present invention provides a method to improvehigh-k dielectric film and metal gate interface in the fabrication ofMOSFET by depositing a metal gate on a high-k dielectric film accordingto any one method of the before described first to fifth aspect of thepresent invention.

A seventh aspect of the present invention provides a substrate treatingsystem comprising a wafer-handling platform including transfer means totransfer a substrate and processing module connected to saidwafer-handling platform; wherein said processing module includes atleast a thermal annealing module and a metal gate deposition module, andsaid transfer means transfer the substrate between said wafer-handlingplatform and said processing module without a vacuum break.

An eighth aspect of the present invention provides a substrate treatingsystem according to the seventh aspect of the present invention whereinsaid processing module further includes a cooling module and/or a high-kdielectric deposition module.

According to an embodiment of the present invention, an improved methodof depositing a metal gate on a high-k dielectric film in thefabrication of MOSFET is provided by which the qualities of high-kdielectric film and metal gate material are improved, thereby theelectron mobility is improved and Vth shift is minimized.

Also, an improved method improving high-k dielectric film and metal gateinterface in the fabrication of MOSFET is provided by which theinterface trap density can be lowered, thereby the electron mobility isimproved and Vth shift is minimized.

Further, a substrate treating system which is suitable to be used in thebefore described methods is provided.

Integration of thermal annealing system and metal gate deposition systemto a one wafer-handling platform improves the high-k dielectric film andmetal gate interface properties and thereby improves electricalcharacteristics and device performance.

BRIEF DESCRIPTIONS OF THE DRAWINGS

FIG. 1 shows a schematic diagram of integrated system used in workingexample one.

FIG. 2 shows another configuration for working example one.

FIG. 3 shows a schematic diagram of working example two.

FIG. 4 shows a schematic diagram of another integrated system.

FIG. 5 shows a cross sectional view of angled-PVD module provided in theintegrated system shown in FIG. 4.

FIG. 6 shows a cross sectional view of thermal annealing module providedin the integrated system shown in FIG. 1.

FIGS. 7( a) to (d) show the procedure of film deposition and thermalannealing process.

FIG. 8 shows a schematic diagram of another integrated system.

FIG. 9 shows a schematic diagram of another integrated system.

FIG. 10 (a) shows uniform-counter lines of Hf film deposited on 300 mmwafer, FIG. 10( b) shows the cross sectional uniformity of Hf film.

FIG. 11 shows a variation of HfSi film composition depending on appliedDC power.

FIG. 12( a) shows uniform-counter lines of TaN film deposited on 200 mmwafer, FIG. 12( b) shows the cross sectional uniformity of TaN film.

FIG. 13 shows RBS data obtained for HfSiON film.

FIG. 14 shows a schematic diagram of wafer treating system in which CVDchamber for depositing high-k dielectrics using CVD technique isconnected to central wafer-handling platform.

FIG. 15 shows a schematic view of MOSFET

EXPLANATION OF REFERENCE SIGNS USED tO DESCRIBE THE PREFERREDEMBODIMENTS

-   1. thermal annealing module-   2. metal gate deposition module-   3. central wafer-handling platform-   4. substrate-   5. wafer alligner-   6. wafer load port-   7. wafer unload port-   8. cooling module-   9. robot arm-   10. high-k dielectric deposition module-   11. angled-PVD module-   12. angled-PVD module-   13. wafer loading/unloading equipment-front-end module-   14. target-   15. target angle α-   16. cathode-   16 a, 16 b, 16 c, 16 d and 16 e. cathodes-   17. substrate holder-   18. central axis of substrate holder-   19. substrate holder-   20. wafer heating mechanism-   21. gas inlet-   22. gas outlet-   23. initially deposited very thin SiO₂ or SiON layer-   24. starting material (film)-   25. high-k dielectric-   26. gate electrode-   27. chamber wall-   28. vacuuming port-   29. wafer in/out port-   30. backing plate-   31. insulator-   32. magnets-   33. substrate in/out port.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of the present invention are described in thefollowing examples in detail using the attached drawings.

Example 1

In FIG. 1, a thermal annealing module 1 and metal gate deposition module2 are connected to a central wafer-handling platform 3, that is to say,a thermal annealing module 1 and metal gate deposition module 2 areintegrated to a central wafer-handling platform 3.

A cross sectional view of the thermal annealing module 1 is shown inFIG. 6. Preferably, the thermal annealing module 1 is a rapid thermalannealing module. The thermal annealing module 1 such as RTP module,shown in FIG. 6, is comprised of a substrate holder 19, a wafer heatingmechanism 20 heating a substrate 4 placed on the substrate holder 19,gas inlet 21, a gas outlet 22 and substrate in/out port 33 as shown inFIG. 6.

Typically, the heating mechanism 20 is an infrared (IR) heating processassisted by IR lamps. Usually, the thermal annealing module 1 such asRTP module can heat a substrate 4 to a temperature around 1000°C. withinseveral seconds. During the substrate heating, substrate holder 19 mayor may not be rotated. The thermal annealing module 1 such as RTP moduleheats a substrate under a low-pressure with an inert gas or mixture ofinert gas and a reactive gas.

The thermal annealing module 1 may employ any suitable technique to heatthe substrate 4 to a higher temperature, for example IR lamps, furnaceannealing, or RF heating. The annealing temperature may vary from 100°C. to 1200° C. . The actual annealing temperature may change dependingon the high-k materials. The annealing pressure is also not critical.The pressure may vary from 10⁻⁷ Pa to atmospheric pressure.

The metal gate deposition technique conducted in the metal gatedeposition module 2 is also not important. The technique may be PVD,thermal CVD or plasma enhanced CVD, or atomic layer deposition. Thedeposition pressure, precursor gas or gas mixtures depend on the type ofmetal gate.

In addition to the thermal annealing and metal gate deposition modules1, 2, a wafer loading/unloading equipment-front-end module 13 isattached to the central platform 3. Therefore, a thermal annealingmodule 1, metal gate deposition module 2 and a wafer loading/unloadingequipment-front-end module 13 are integrated to a central wafer-handlingplatform 3. The wafer loading/unloading equipment-front-end module 13comprises a wafer aligner 5, wafer load port 6 and unload port 7.

The substrate 4 with high-k dielectric film deposition thereon is placedin the thermal annealing module 1 in FIG. 1. Substrate 4 is thensubjected to thermal annealing process in the thermal annealing module 1at a desired temperature. The thermal annealing may be a single step ora two-step process with different gas atmospheres.

Then, substrate 4 is transferred into the metal gate deposition module 2via the central wafer-handling platform 3 by the transfer means such asrobot arm 9. And in the metal gate deposition module 2, metal gatematerial is deposited. The metal gate material may be any suitablematerial with appropriate electrical properties. For example metal gatematerial may be TaN, HfSi , RuTa, Ir, W, etc.

As described before, the annealing step annealing a substrate withhigh-k dielectric film deposited thereon in a thermal annealing moduleand depositing step depositing a metal gate material on said annealedsubstrate in a metal gate deposition module are carried outconsecutively without a vacuum break.

FIG. 2 shows that a cooling module 8 is connected to the centralwafer-handling platform 3 in addition to the configuration shown inFIG. 1. That is to say, in FIG. 2, a thermal annealing module 1, metalgate deposition module 2, a cooling module 8 and a waferloading/unloading equipment-front-end module 13 are integrated to acentral wafer-handling platform 3.

Using the integrated system shown in FIG. 2, after the thermal annealingof high-k dielectric mentioned above, one can cool down the substrate 4before placing it inside the metal gate module 2.

That is to say, using the integrated system shown in FIG. 2, firstlyconducting an annealing step annealing a substrate with high-kdielectric film deposited thereon in a thermal annealing module, thencooling said annealed substrate in a cooling module, and then depositinga metal gate material on said cooled substrate in a metal gatedeposition module, wherein said annealing step, cooling step anddepositing step can be carried out consecutively without a vacuum break.

As described before, the thermal annealing module and metal gatedeposition module are integrated to a single central wafer-handlingplatform, so that immediately after the high-k annealing process, waferscan be transferred into metal gate deposition module without a vacuumbreak and deposit metal gate.

Also, the thermal annealing module, the cooling module, and metal gatedeposition module are integrated to a single central wafer-handlingplatform, so that immediately after the high-k annealing process andcooling process, wafers can be transferred into the metal gatedeposition module without a vacuum break and deposit metal gate.

Integration of thermal annealing system and metal gate deposition systemto a one central wafer-handling platform, or integration of thermalannealing system, cooling system and metal gate deposition system to aone central wafer-handling platform can improve the high-k dielectricfilm and metal gate interface properties and thereby improve electricalcharacteristics and device performance.

Example 2

FIG. 3 shows an example which is an extension of working example 1,wherein there is an additional high-k dielectric deposition module 10attached to the central wafer handling platform 3 described in workingexample 1.

In the example shown in FIG. 3, a high-k dielectric deposition module 10is connected to the central wafer-handling platform 3 in addition to theconfiguration shown in FIG. 2. That is to say, in FIG. 3, a thermalannealing module 1, metal gate deposition module 2, a cooling module 8,a high-k dielectric deposition module 10 and a wafer loading/unloadingequipment-front-end module 13 are integrated to a central wafer-handlingplatform 3.

A cooling module 8 may be removed from the configuration shown in FIG.3.

The high-k dielectric deposition technique can be any desired technique,for example PVD, CVD, MOCVD or ALD. The parameters such as depositionpressure, precursor gases, temperature etc., depend on the type ofdeposition technique and high-k material.

First, high-k dielectric, for example HfO₂, is deposited on a substrate4 by placing a wafer in high-k dielectric deposition module 10. One canalso deposit a metal or metal alloy in the high-k deposition module 10,for example Hf, HfSi, HfAl etc., to be oxidized in the thermal annealingmodule 1. The substrate 4 is then transferred into the thermal annealingmodule 1 and performs the annealing process. The annealing is usually asingle step in oxygen or in an inert gas environment. One can however,carry on a two-step annealing process where in the first step annealingis done in an oxygen atmosphere at relatively a lower temperature, whilein the second step annealing is done in an inert gas environment atrelatively a higher temperature.

Then by using the cooling module 8, the wafer is cooled down.Thereafter, the wafer is transferred into metal gate deposition module2, and deposits a metal.

When the configuration given in FIG. 3 is used, high-k deposition,thermal annealing and metal gate deposition can be done without a vacuumbreak. This results in further improvement of film quality and therebysemiconductor device quality.

Using the integrated system shown in FIG. 3, the following process canbe conducted. Firstly, depositing a high-k dielectric film on asubstrate in a high-k deposition module, annealing said substrate onwhich high-k dielectric film is deposited in a thermal annealing module,cooling said annealed substrate in a cooling module, and then depositinga metal gate material on said cooled substrate in a metal gatedeposition module wherein said first depositing step, annealing step,cooling step and second depositing step are carried out consecutivelywithout a vacuum break.

Also, the following process can be conducted. After the first depositingstep depositing a thin thermal SiO₂ film on a substrate in a thermalannealing module, cooling said substrate in a cooling module, depositinga high-k dielectric film on said substrate in a high-k depositionmodule, annealing said substrate in a thermal annealing module, coolingsaid annealed substrate in a cooling module, and then depositing a metalgate material on said cooled substrate in a metal gate deposition modulewherein said first depositing step, first cooling step, seconddepositing step, annealing step, second cooling step and thirddepositing step are carried out consecutively without a vacuum break.

As described before, the thermal annealing module, the cooling module,the high-k deposition module, and the metal gate deposition module areintegrated to a single central wafer-handling platform, so thatimmediately after the high-k annealing process and cooling process,wafers can be transferred into metal gate deposition module without avacuum break and deposit metal gate.

Integration of the thermal annealing system, the cooling module, thehigh-k deposition module, and the metal gate deposition module to a onecentral wafer-handling platform can improve the high-k dielectric filmand the metal gate interface properties and thereby improves electricalcharacteristics and device performance.

Example 3

FIG. 4 shows a schematic diagram of the integrated system comprised oftwo angled-PVD modules 11 and 12, one thermal annealing module 1, acooling module 8, a central wafer-handling platform 3, and a waferloading/unloading equipment-front-end module 13.

The hardware configuration of both angled-PVD systems 11 and 12 are thesame except the target materials fixed to each cathode. A crosssectional diagram of an example of an angled-PVD module which can beadopted in the substrate treating system of the present invention isshown in FIG. 5.

The angled-PVD module 11 and 12 is comprised of a chamber having achamber wall 27, a vacuuming port 28 and a wafer in/out port 29. Thesubstrate holder 17 is provided in the chamber as shown in FIG. 5.

The angled-PVD modules 11 and 12 employ off-axis sputtering technologywhere substrate 4 and target 14 surfaces are not parallel as inconventional PVD systems. Instead these two surfaces make an angle a(denoted by numeral 15) as shown in FIG. 5. This angle α(15) is however,not critical and can lie in the range of 10° to 90°, but typically liesaround 45°. Each angled-PVD system may have one or more angled targets.For example, as one cathode 16 is shown in FIG. 5, each PVD system shownin FIG. 4 accommodates 5 cathodes (16 a, 16 b, 16 c, 16 d and 16 e) andthereby 5 targets 14.

In each cathode, as shown in FIG. 5, backing plate 30 is provided on theopening of cathode 16 by insulator 31. Target 14 is supported by thefront side of the backing plate 30, and magnets 32 are provided at theback side of backing plate 30. The magnets 32 are rotated during filmdeposition.

A target 14 made of a metal, metal nitride or metal oxide or asemiconductor is fixed to each cathode 16 a to 16 e. Each cathode issupplied with a DC, as shown in FIG. 5, or RF electrical power to igniteand maintain a plasma. The ions in the plasma sputter the targetmaterial and these sputtered atoms are deposited on the substrate 4placed on substrate holder 17.

The substrate holder 17 where a substrate 4 is placed for the filmdeposition rotates around its central axis 18 during film deposition.The rotation of substrate holder 17 is of importance to obtain a uniformfilm thickness over the wafer surface since sputtered atoms are comingwith an angle.

The PVD module can accommodate 5 cathodes (16 a, 16 b, 16 c, 16 d, 16 e)at the same time. These cathodes 16 a to 16 e are fixed to the ceilingof the angled PVD modules 11 and 12 respectively with an angle α(15)with respect to the surface of substrate 4. This angle α(15) is notcritical and can be varied in the range of 0 to 90°, but typically liesaround 45°. In each cathode 16, there is a metal or dielectric target 14as an integrated part of the cathode 16. Above the target 14, there is amagnet 32, which is rotated during film deposition. The magnet 32however, is not essential. Use of magnet 32 increases the plasma densityand confines the plasma to the region below the target suppressingdiffusion towards the wall 27 of the chamber of PVD module. The diameterof a target 14 is also not critical and is usually around 200 mm. Thetarget 14 is simply a planar plate firmly fixed to a backing plate 30.The backing plate 30 is usually cooled using circulating water or anyother suitable liquid. The cooling mechanism of the backing plate 30 isnot shown for the clarity of the diagram.

In FIG. 5 numeral 35 indicates a shutter.

Each cathode 16 is electrically isolated from the rest of the hardwareand connected to a DC or RF electrical supply unit. In FIG. 5 only a DCpower source is shown. The DC or RF power applied to a target 14 is notcritical but typically lies lower than 500 W. The reason is high-kmaterials that should be deposited on a substrate 4 should be very thin.Therefore, in order to control the film thickness to a greater accuracy,film deposition rate must be lowered. So that, by measuring thedepositing time, film thickness can be controlled accurately.

The angled PVD modules 11 and 12 are vacuumed to a lower pressure andmaintained at a low-pressure before and after plasma is ignited. Theinside pressure in the chamber of angled PVD modules 11 and 12 is notcritical, however, deposition is usually carried out at a pressure lowerthan 1 Pa.

It is possible to obtain extremely uniform depositing film, byconsidering and comparing the mean-free-path of gas atoms in the PVDmodules 11 and 12 with respect to the substrate-to-target distance.

The sputter deposition can be carried out with the use of an inert gasplasma, such as Ar plasma or using a gas mixture such as Ar+O₂ or Ar+N₂.When a reactive gas mixture is used, sputtered atoms react with thegaseous species and form a different product such as metal nitride oroxide and then are deposited on the water surface. The film depositionis usually carried out at a pressure lower than 1 Pa, however, as thisis not critical, one can use a different pressure for the filmdeposition.

The film deposition can be done using a single target 14 by supplying DCor RF power to that appropriate target. Or, film deposition can be doneby a co-sputtering process where RF or DC power is supplied to two orseveral targets 14, which are provided at each cathode 16 a to 16 e, atthe same time. In this case, the atomic composition of alloy material iscontrolled by adjusting the DC or RF electrical power applied to eachtarget.

One of the angled-PVD systems may be used for high-k dielectrics whilethe other may be used for gate electrode deposition.

The thermal annealing module 1 used in the configuration of FIG. 4 isthe same as shown in FIG. 6 and described in Example 1.

When a substrate 4 with a film deposited in angled PVD module 11 isplaced in the thermal annealing module 1 such as RTP module, it isheated to a higher temperature usually over 400° C. under a reactive gasmixture, preferably with Ar+O₂ gas mixture. During this heating, themetal, metal-alloy or metal nitride films get oxidized and become adielectric.

The heating by the thermal annealing module 1, such as RTP module, canbe carried out in two or more steps under the same or different gasenvironments. In the first step, for example heating is carried out onlyto oxidize the film deposited on a wafer surface, and in the second orlater steps wafer is heated to even a higher temperature to mix theoxidized film with underlying Si or any other underlying film.

The cooling module 8 is comprised of at least a wafer stage cooled to alower temperature.

Again, there may be an electrostatic chuck mechanism integrated to thewafer stage to clamp the wafer on to the wafer stage. This is importantif the wafer cooling must be done at a higher rate. The pressure insidethe cooling module 8 is not important and can be in the range ofatmospheric pressure to lower pressures as low as 10⁻⁷ Pa.

The central wafer-handling platform 3 includes a transfer means such asa robot arm 9 that delivers substrate 4 between angled PVD module 11 andcentral wafer-handling platform 3, thermal annealing module 1 andcentral wafer-handling platform 3, angled PVD module 12 and centralwafer-handling platform 3, cooling module 8 and central wafer-handlingplatform 3, and wafer loading/unloading equipment-front-end module 13and central wafer-handling platform 3, respectively, without a vacuumbreak.

The wafer loading/unloading equipment-front-end module 13 is alsocomprised of at least a wafer handling robot arm and one or severalstages to place wafer cassettes. These are not shown in figures forsimplicity.

A method of high-k and metal gate preparation is as follows andexplained with reference to FIG. 7.

Step-1 Deposit preliminary film for high-k dielectricStep-2 Thermally anneal under oxygen atmosphere to form high-kdielectricStep-3 Cool down the waferStep-4 Deposit metal electrode material.Detailed description of the deposition method:

Step-1

The starting wafer may or may not have an initially deposited very thinSiO₂ or SiON layer 23. This is shown in FIG. 7( a).

A starting material 24 for high-k dielectric is deposited on substrate 4using one of the angled-PVD modules (FIG. 7( b)). The starting material24 may be a metal, preferably refractory metal such as Hf, Ta, Zr etc.,metal nitride such as HfN, TaN, TiN etc., metal alloy such as HfTa,HfTi, etc., metal-semiconductor alloy such as HfSi etc. or metal alloynitrides such as TaSiN etc.

Again, one can deposit two or several films mentioned above as a stackedconfiguration. For example, Hf/SiN/Hf, HfN/AIN, Hf.

Usually, Hf, Zr, Ti, or Ta is used as a metal target 14. However, othermetal targets can be used. In case a metal-semiconductor alloy isdeposited, preferably the semi-conducting material is Si.

Though it is not critical, the film thickness of the above startingmaterials is usually kept less than 5 nm, typically around 2 nm.

Step-2

After the deposition of starting film 24 as described above, substrate 4is transferred to thermal annealing module 1. The substrate 4 is heatedto a higher temperature usually over 400□, under an oxygen gasatmosphere, so that starting material gets oxidized (FIG. 7( c)) forminga high-k dielectric 25. The heating process can be carried out as asingle step or several steps. Usually, a heating procedure with twosteps or several steps is more suitable to control the chemical reactionduring annealing process. For example, first the film is heated to 400□to oxidize the metallic elements in the starting material. If the filmis heated to a very high temperature at once, for example to 800□,metallic elements in the film may form their silicides, which are stableand show metallic features. Once the film is properly oxidized at arelatively lower temperature such as 400□, temperature is raised to ahigher value, for example to 900□, preferably in an inert gasenvironment. If metal stacks of different metals are used as thestarting material, high-temperature annealing is important forinter-diffusion of each material and to form a uniform film composition.

Step-3

After completion of thermal annealing process, substrate 4 istransferred to the cooling module 8 and cooled to a desired temperature,preferably to the room temperature.

Step-4

The substrate 4 is transferred to the other angled-PVD module anddeposited a gate electrode 26 (FIG. 7( d)).

The gate material may be a metal such as Ta, Ru, Hf etc., a metalnitride such as TiN, HfN, TaN etc., metal alloy such as RuTa, HfTa,etc., metal semiconductor alloy such as HfSi, TaSi etc., metalsemiconductor alloy nitrides such as TaSiN etc. or a stack of abovementioned films such as Hf/TaN/TiN, Ru/Ta/TaN etc.

In depositing film stack one on each other, substrate does not have tobe removed from the angled-PVD module to deposit each film. Since thisPVD module has five cathodes 16 a to 16 e and supports up to 5 differenttargets, by fixing appropriate targets one can deposit any desired metalstacks in the same angled-PVD module.

After the gate electrode deposition, the substrate may subject tothermal annealing process, particularly if metal stacks are deposited.During this thermal annealing process, metal stacks inter-diffuse andform a new uniform composition. Otherwise, one can take the waferdirectly out from the integrated system shown in FIG. 4 after the gateelectrode deposition.

Preferably, before placing a wafer in the above integrated system, thesubstrates are treated as follows to get improved electrical properties.

1. The substrate is cleaned with diluted HF solution to remove nativeoxide on the surface

2. Dry the substrate

3. Deposit very thin layer of thermal SiO₂ (eg. 1 nm) (eg. Initiallydeposited film 23 shown in FIG. 7( a)). This process can be conducted inthe thermal annealing module 1.

The reason for the use of thin SiO₂ layer 23 on Si substrate 4 is thatafter the preparation of overall film deposition process asdescribed-above, a fraction of originally deposited SiO₂ layer 23remains at interface between Si substrate 4 and high-k dielectric 25 asshown in FIG. 7( c) and 7(d). This results in a lower leakage current,lower voltage hysterias, and improved electron mobility in the channelregion in a MOSFET.

These angled PVD modules give 11, 12 shown in FIG. 5 and used in theconfiguration of FIG. 4 can achieve higher deposition rate. As a resultof higher deposition rate, an economically viable throughput can beobtained by the present invention.

Example 4

In FIG. 8, there are two angled PVD modules 11 ad 12, two thermalannealing modules 1 a and 1 b, one cooling module 8 and waferloading/unloading equipment front-end module 13 attached to a centralwafer-handling platform 3.

Compared to the integrated system explained in working example 3, thereis an additional thermal annealing module in this working example 4.Except for this addition, all the other hardware are the same as thatexplained in working example 3. This additional thermal annealing moduleis used for high-temperature annealing of gate electrode material. Useof separate thermal annealing modules to anneal starting material toform high-k dielectric and gate electrode, increases the throughput andminimize cross contamination. Except for the above-mentioned difference,all the other processing steps and procedures are the same as thatexplained in working example 3.

Example 5

FIG. 9 shows a schematic diagram of the integrated system for thedeposition of high-k dielectric, which is comprised of angled PVD module11, thermal annealing module 1 such as RTP module, centralwafer-handling platform 3 and a wafer loading/unloadingequipment-front-end module (EFEM) 13.

The construction and mechanism of the angled PVD module 11 is describedin Example 3 and shown in FIG. 5. So that, they are omitted from thisexample.

FIG. 10( a) shows a Hf film uniformity deposited on a 300 mm wafer at apressure of 0.015 Pa using the angled PVD module 11. The otherparameters used for that deposition are as follows. Target-to-substratevertical distance=250 mm, DC power applied to Hf target=300 W, substrateholder rotation speed=240 rpm, Plasma gas=Ar. The standard deviation (σ)of larger number of film thickness measurements is usually given as thefilm non-uniformity. The standard deviation (σ) of 49-points measurementon Hf film given in FIG. 10( a) is 0.16%. The lines shown in FIG. 10( a)are the constant-uniform contours 36. The numeral 37 given at eachcontours is the normalized uniformity. FIG. 10( b) shows the normalizeduniformity across a diameter line.

In case of bi-metal or metal alloy depositions, two or many targets (16a, 16 b,) are given DC or RF power simultaneously. By adjusting the DCor RF power applied to each cathode, the composition of metal alloy canbe varied. For example FIG. 11 shows controllability of HfSicomposition. The deposition condition for FIG. 11 is as follows.

Process gas=Ar, Pressure=0.015 Pa, Hf target DC power=70 W, Si target DCpower=30 W to 130 W, Substrate-to-target distance=250 mm. The Hffraction of HfSi film can be controlled from 55% to 82% (or Si fractionfrom 45% to 18%) by controlling the DC power applied to Si target. InFIG. 11, variation of Hf fraction in HfSi film is denoted numeral 38 andvariation of Si fraction in HfSi film is denoted numeral 39.

In case of reactive sputter depositions, a reactive gas, for exampleoxygen or nitrogen is added to the PVD module in addition to an inertgas, for example Ar. The reactive gas decomposes in the plasma andreacts with the sputtered atom and then deposits on the wafer surface.For example, FIG. 12( a) shows film uniformity of TaN film deposited byreactive sputtering method using Ar+N₂ gas mixture with the followingcondition.

Ta target DC power=300 W, Plasma gas=Ar, Pressure=0.015 Pa, Ar flowrate=30 sccm, N₂ flow rate=10 sccm, substrate-to-target distance=250 mm.

FIG. 12( a) shows the constant uniform contours 36 while FIG. 12( b)shows the normalized uniformity across a diameter line. The standarddeviation of 49-thickness measurement on TaN film shown in FIG. 12 is0.13%.

After a film is deposited in PVD module 11, substrate 4 is transferredto the thermal annealing module 1 without a vacuum break.

The thermal annealing module 1 is an RTP module shown in FIG. 6 anddescribed in the before described example 1.

The heating by the thermal annealing module 1 such as RTP module can becarried out in two or more steps under the same or different gasenvironments. In the first step, for example, heating is carried outonly to oxidize the film deposited on a wafer surface, and in the secondor later steps wafer is heated to an even higher temperature to mix theoxidized film with underlying Si or any other underlying film.

For example, HfSiON film is fabricated with the following procedure.

Started with p-type Si wafer

Cleaned with HF to remove native oxide

Deposited 1 nm thermal SiO₂

Deposited 1 nm HfN by placing in the PVD module (11)

Placed wafer in RTP module (1)

Annealed at 400 for 30 sec. in an oxygen ambient

Annealed at 800 for 30 sec. in an inert gas ambient

Wafer is taken out and film is evaluated.

During the first annealing step HfN film gets oxidized and form HfON.During the second annealing step, HfON and underlying SiO₂ film getsintermixed and form HfSiON. RBS spectra obtained for the above film isshown in FIG. 13, which clearly shows the film is HfSiON.

It should be noted that after the RTP process, a Ti film is deposited asa capping layer to prevent further oxidation of prepared high-k film.

During the second RTP process only a fraction of initially depositedthermal SiO₂ film is consumed to form HfSiON. Therefore, a thin SiO₂layer remains below the HfSiON film just above the semiconductor.

It is important to have a very thin layer of thermal SiO₂ remainingbelow the HfSiON film to improve the electron mobility in the channelregion 107 (FIG. 15). So that one has to control the RTP temperature andtime to consume only a fraction of thermal SiO₂. By this method, one cantherefore, have very thin thermal SiO₂ layer, for example 5 angstrom,under HfSiON layer. The importance of this process is that there is noreliable technique in directly depositing such a thin SiO₂ layer.

HfSiON is considered as a high-k material with a relative dielectricconstant between 15-24 depending on film composition.

Similar to the method explained above, one can deposit many otherdifferent high-k materials using PVD module and RTP module withouthaving a vacuum-break.

Since this process does not involve vacuum-break, the overall process isvery reliable and repeatable, so that this process can be confidentlyapply in actual device fabrications.

As described before, a PVD (physical vapor deposition) module and RTP(rapid thermal processing) module are integrated together with the useof wafer transfer module and EFEM (equipment front-end module), whereinfirst a metal, metal nitride or metal oxide film is deposited on asubstrate by placing in PVD module and secondly the wafer is subjectedto RTP process to convert metal film into dielectric and/or improvedielectric properties. The film deposition step and RTP process iscarried out without a vacuum break so that film deposited by thisprocedure gives repeatable and reliable properties.

The present invention is not limited to the preferable examplesdescribed above, and may be modified to various embodiments within thetechnological scope defined by the accompanying claims and equivalentsthereof.

1. A substrate treating system comprising a wafer-handling platformincluding a transfer device to transfer a substrate and a processingmodule connected to said wafer-handling platform; wherein saidprocessing module includes at least a thermal annealing module and ametal gate deposition module; and said transfer device is adapted totransfer the substrate between said wafer-handling platform and saidprocessing module without a vacuum break.
 2. The substrate treatingsystem according to claim 1, wherein said processing module furtherincludes a cooling module or a high-k higher dielectric materialdeposition module.
 3. The substrate treating system according to claim1, wherein said processing module further includes a cooling module anda high-k higher dielectric material deposition module.
 4. A substratetreating apparatus comprising: an angled-PVD module configured andpositioned to deposit a starting material on a substrate; a thermalannealing module configured and positioned to anneal a substrate onwhich the starting material is deposited; and a transfer deviceconfigured and positioned to deliver the substrate to the angled-PVDmodule and the thermal annealing module.